1. Field of the Invention
The present invention relates generally to a electrically erasable and programmable read only memory (single-level EEPROM), and more particularly to a single-level electrically erasable and programmable read only memory (single-level EEPROM) operated in environment with high/low-voltage.
2. Description of the Prior Art
As semiconductor devices, such as the Metal-Oxide-Semiconductor device, become highly integrated the area occupied by the device shrinks, as well as the design rule. With advances in the semiconductor technology, the dimensions of the integrated circuit (IC) devices have shrunk to the deep sub-micron range. When the semiconductor device continuously shrinks in the deep sub-micron region, some problems described below are incurred due to the scaling down process. To meet customer demand for small size and low power products, manufacturers are producing newer integrated circuits (ICs) that operate with various supply voltages and that include smaller internal sub-circuits. Many ICs, such as memory circuits or other circuits such as microprocessors that include onboard memory, include one or more Electrically erasable and programmable read only memory(EEPROM)cells for data storage.
Electrically erasable and programmable read only memory (EEPROM) is currently one the most widely used memory devices applied in personal computers and electronic equipment. A memory cell in an early developed conventional EEPROM comprises a transistor with a floating gate to achieve the operations of writing, erasing, and storing data while electrical shut down. This conventional memory cell typically occupies a large surface area and the data access speed is between 150 ns to 200 ns, but the lately developed memory cell has a faster data access speed ranged between 70 ns to 80 ns. While storing data, a high voltage of 8V is applied between the drain region and the source region. Meanwhile, the controlling gate is biased with the same high voltage. The hot electrons thus flow out of the source region and toward the drain region. While approaching the drain region, these hot electrons tunnel through the oxide layer and are trapped in the floating gate. This is known as the drain side injection operation. By applying a positive voltage to the source region and a negative voltage to the controlling gate, the electrons trapped in the floating gate flow out of the floating gate and tunnel through the oxide layer. Thus the stored data are erased and the floating gate is retrieved to the status before data storing.
In general, conventional electrically erasable programmable read only memory (EEPROM) is a double-level electrically erasable programmable read only memory device with two poly-gate that utilizes dual field effect transistors(FET)to control current flow through a channel region between source and drain regions. This double-level EEPROM includes: a floating gate, formed from a first layer of polycrystalline silicon, overlays the channel region; a control gate, formed from a second layer of polycrystalline silicon, overlays the floating gate. To read the memory cell, the control gate is typically charged to draw electrons into the channel and to permit current flow. However, this effect may be blocked by the floating gate positioned between the channel and the control gate. The floating gate influences the current flow in the channel as a function of the charge trapped on the floating gate. This double-level EEPROM cell is programmed by tunneling charge carriers on or off the floating gate with suitably applied electric fields that act across thin oxide layers; the size and thickness of the thin oxide layers are critically important to proper operation of the device. More introduction of double-level EEPROM cell can be acquired by referring to U.S. Pat No. 4,477,825, issued Oct. 16, 1984 disclosed by Yaron et al.
Recently, another electrically erasable programmable read only memory (EEPROM) has been developed to form a single-level electrically erasable programmable read only memory device with one poly-gate. Single-level EEPROM is widely used as nonvolatile memory for embedded applications in CMOS logic and mixed signal circuits. In a single-level EEPROM device, both the floating gate and the control gate function are performed by a single polycrystalline silicon layer. In general, the floating gate function and the control gate function are performed by different areas of the single poly layer. Capacitive coupling between the floating gate and the control gate is used to transfer a switch voltage from the control gate to the floating gate so as to permit the write/erase operation of the floating gate. On the other hand, the single-level EEPROM cell is fully compatible with standard single poly CMOS processes. The conventional single-level EEPROM cell comprises: an n-well served as a control gate for the EEPROM cell; a floating gate which is formed from a polysilicon layer, wherein the control gate is capacitively coupled to the floating gate; a p+ region in the n-well near the edge of the floating gate is shorted with a n+ well contact. This allows the n-well surface beneath the floating gate to be easily inverted during programming operation. The n-channel transistor is used for the read operation and its threshold voltage is modulated by the presence or absence of electron charge on the floating gate. By this method, digital information can be stored in the single-level EEPROM cell. Furthermore, single-level EEPROM cell can be programmed, that is, electrons injected onto the floating gate, using the well known channel hot electron (CHE) injection by applying approximately 10-12 volts at the control gate (Vcg) and approximately 6 volts at the drain of the n-channel transistor. After programming, the threshold voltage of the memory cell is increased from about 1 to 3 volts to over 7 volts. Thus, for read operation, by applying 5 volts on the control gate and approximately 1 volt at the drain, the cell is either “off” or “on” representing the digital information “0” or “1”, respectively.
Recently, in the circuit design rule for, the requirement for utilizing the relatively electric-field with a wide range is increased day by day, that is, the circuit design rule for utilizing the relatively positive and negative voltages with a wide range is more and more necessary. For example of Thin-Film Transistor Liquid-Crystal Display (TFT-LCD) or Super-Twisted Nematic Liquid Crystal Display (STN-LCD), if the positive and negative voltages with a wide range can be provided to operate the drivers thereof, various colors and brightness will be generated. However, the common process for forming the single-level EEPROM as well known belongs to the twin-well process, and this single-level EEPROM is only utilized in designated field so that it is difficult to develop widely. The main reason is that the MOS device operated in environment with high voltage can not be embedded on the twin-well process for forming the single-level EEPROM. Therefore, it is necessary that another circuitry is additionally designed in the prior art so as to control or convert operation between positive and negative voltages, whereby the positive voltage is inputted into the conventional circuitry first, and another circuitry converts it into the negative voltage to output. Accordingly, disadvantages are not only complex process for forming this prior circuitry, but also high power consumption and large in size for design applications. The main difficulty is that the single-level EEPROM cell for operating in environment with relatively positive and negative voltages can not be fabricated by the conventional process. In accordance with the above description, a new and improved process and the structure thereof of the single-level EEPROM for operating in environment with relatively positive and negative voltages is therefore necessary in the deep sub-micron technology of semiconductors, so as to raise the performance of the single-level EEPROM.